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| a FEATURES FET Input Amplifier 1 pA Input Bias Current Low Cost High Speed 145 MHz, -3 dB Bandwidth (G = +1) 180 V/ s Slew Rate (G = +2) Low Noise 7 nV/Hz (f = 10 kHz) 0.6 fA/Hz (f = 10 kHz) Wide Supply Voltage Range 5 V to 24 V Single-Supply and Rail-to-Rail Output Low Offset Voltage 1.5 mV Max High Common-Mode Rejection Ratio -100 dB Excellent Distortion Specifications SFDR -88 dB @ 1 MHz Low Power 6.4 mA/Amplifier Typical Supply Current No Phase Reversal Small Packaging SOIC-8, SOT23-5, and MSOP APPLICATIONS Instrumentation Photodiode Preamp Filters A/D Driver Level Shifting Buffering High Performance, 145 MHz Fast FET TM Op Amps AD8065/AD8066* CONNECTION DIAGRAMS SOIC-8 (R) NC 1 -IN 2 +IN 3 -VS 4 SOT23-5 (RT) VOUT 1 -VS 2 +IN 3 TOP VIEW (Not to Scale) 4 -IN AD8065 8 NC 7 +VS 6 VOUT AD8065 5 +VS TOP VIEW 5 NC (Not to Scale) NC = NO CONNECT SOIC-8 (R)1 and MSOP (RM) VOUT1 1 -IN1 2 +IN1 3 -VS 4 (Top View) 8 7 6 5 AD8066 +VS VOUT2 -IN2 +IN2 Despite being low cost, the amplifiers provide excellent overall performance. The differential gain and phase errors of 0.02% and 0.02, respectively, along with 0.1 dB flatness out to 7 MHz, make these amplifiers ideal for video applications. Additionally, they offer a high slew rate of 180 V/s, excellent distortion (SFDR -88 dB @ 1 MHz), extremely high commonmode rejection of -100 dB, and a low input offset voltage of 1.5 mV max under warmed up conditions. The AD8065/ AD8066 operate using only 6.4 mA/amplifier typical supply current, while they are capable of delivering up to 30 mA of load current. The AD8065/AD8066 are high performance, high speed, FET input amplifiers available in small packages: SOIC-8, MSOP, and SOT23-5. They are rated to work over the industrial temperature range of -40C to +85C. 24 G = +10 21 VO = 200 mVp-p 18 G = +5 15 GENERAL DESCRIPTION The AD8065/AD8066 Fast FET amplifiers are voltage feedback amplifiers with FET inputs offering very high performance and ease of use. The AD8065 is a single amplifier and the AD8066 is a dual amplifier. The Fast FET amplifiers in ADI's proprietary XFCB process allow exceptionally low noise operation (7.0 nV/Hz and 0.6 fA/Hz) as well as very high input impedance. With a wide supply voltage range from 5 V to 24 V, the ability to operate on single supplies, and bandwidth of 145 MHz, the AD8065/ AD8066 are designed to work in a variety of applications. For added versatility, the amplifiers also contain rail-to-rail outputs. GAIN - dB 12 9 G = +2 6 3 G = +1 0 *Protected by U.S. Patent No. 6262633 1 Under development Fast FET is a trademark of Analog Devices, Inc. -3 -6 0.1 1 10 FREQUENCY - MHz 100 1000 REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Figure 1. Small Signal Frequency Response One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002 AD8065/AD8066-SPECIFICATIONS (@ T = 25 C, V = A S 5 V, RL = 1 k , unless otherwise noted.) Typ 145 120 50 42 7 175 170 180 55 205 -88 -67 73 24 7 0.6 0.02 0.02 0.4 1 2 25 1 1 113 1000 2.1 1000 4.5 1.5 17 6 10 Max Unit MHz MHz MHz MHz MHz ns ns V/s ns ns dBc dBc dBc dBm nV/Hz fA/Hz % Degree mV V/oC pA pA pA pA dB G pF G pF V V dB dB V V mA mA pF 24 7.2 V mA dB Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Conditions G = +1, VO = 0.2 V p-p (AD8065) G = +1, VO = 0.2 V p-p (AD8066) G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p G = +2, VO = 0.2 V p-p G = +1, -5.5 V to +5.5 V G = -1, -5.5 V to +5.5 V G = +2, VO = 4 V Step G = +2, VO = 2 V Step G = +2, VO = 8 V Step Min 100 100 Bandwidth for 0.1 dB Flatness Input Overdrive Recovery Time Output Recovery Time Slew Rate Settling Time to 0.1% 130 NOISE/HARMONIC PERFORMANCE SFDR fC = 1 MHz, G = +2, VO = 2 V p-p fC = 5 MHz, G = +2, VO = 2 V p-p fc = 1 MHz, G = +2, VO = 8 V p-p Third Order Intercept fC = 10 MHz, RL = 100 Input Voltage Noise f = 10 kHz Input Current Noise f = 10 kHz Differential Gain Error NTSC, G = +2, RL = 150 Differential Phase Error NTSC, G = +2, RL = 150 DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Usable Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio TMIN to TMAX VO = 3 V, RL = 1 k 100 VCM = 0 V, SOIC Package SOIC Package TMIN to TMAX 5 to +1.7 See Applications section VCM = -1 V to +1 V VCM = -1 V to +1 V (SOT23) RL = 1 k RL = 150 VO = 9 V p-p, SFDR -60 dBc, f = 500 kHz 30% Overshoot G = +1 5 PSRR 85 -85 -82 -4.88 to +4.90 -5.0 to +2.4 -5.0 to +5.0 -100 -91 4.94 to +4.95 4.8 to +4.7 35 90 20 6.4 -100 -2- REV. A AD8065/AD8066 SPECIFICATIONS (@T = 25 C, V A S = 12 V, RL = 1 k , unless otherwise noted.) Conditions G = +1, VO = 0.2 V p-p (AD8065) G = +1, VO = 0.2 V p-p (AD8066) G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p G = +2, VO = 0.2 V p-p G = +1, -12.5 V to +12.5 V G = -1, -12.5 V to +12.5 V G = +2, VO = 4 V Step G = +2, VO = 2 V Step G = +2, VO = 10 V Step fC = 1 MHz, G = +2, VO = 2 V p-p fC = 5 MHz, G = +2, VO = 2 V p-p fc = 1 MHz, G = +2, VO = 10 V p-p fC = 10 MHz, RL = 100 f = 10 kHz f = 10 kHz NTSC, G = +2, RL = 150 NTSC, G = +2, RL = 150 VCM = 0 V, SOIC Package SOIC Package TMIN to TMAX TMIN to TMAX VO = 10 V, RL = 1 k 103 Min 100 100 Typ 145 115 50 40 7 175 170 180 55 250 -100 -67 -85 24 7 1 0.04 0.03 0.4 1 3 25 2 2 114 1000 2.1 1000 4.5 12 to +8.5 -12.0 to +9.5 -12.0 to +12.0 85 -100 -82 -91 -11.8 to +11.8 11.9 to +11.9 11.25 to +11.5 30 120 25 5 PSRR 84 6.6 -93 24 7.4 1.5 17 7 10 Max Unit MHz MHz MHz MHz MHz ns ns V/s ns ns dBc dBc dBc dBm nV/Hz fA/Hz % Degree mV V/oC pA pA pA pA dB G pF G pF V V dB dB V V mA mA pF V mA dB Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Input Overdrive Recovery Output Overdrive Recovery Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE SFDR 130 Third Order Intercept Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Usable Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio See Applications section VCM = -1 V to +1 V VCM = -1 V to +1 V (SOT23) RL = 1 k RL = 350 VO = 22 V p-p, SFDR -60 dBc, f = 500 kHz 30% Overshoot G = +1 REV. A -3- AD8065/AD8066-SPECIFICATIONS (@ T = 25 C, V = 5 V, R = 1 k A S L to 1.5 V, unless otherwise noted.) Min Typ 155 130 50 43 6 175 170 160 60 65 50 22 7 0.6 0.13 0.16 0.4 1 1 25 1 1 113 103 1000 2.1 1000 4.5 0 to 1.7 1.5 17 5 5 Max Unit MHz MHz MHz MHz MHz ns ns V/s ns dBc dBc dBm nV/Hz fA/Hz % Degree mV V/oC pA pA pA pA dB dB G pF G pF V V dB dB V V mA mA pF 24 7.0 V mA dB Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Conditions Bandwidth for 0.1 dB Flatness Input Overdrive Recovery Time Output Recovery Time Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE SFDR Third Order Intercept Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range FET Input Range Usable Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio G = +1, VO = 0.2 V p-p (AD8065) 125 G = +1, VO = 0.2 V p-p (AD8066) 110 G = +2, VO = 0.2 V p-p G = +2, VO = 2 V p-p G = +2, VO = 0.2 V p-p G = +1, -0.5 V to +5.5 V G = -1, -0.5 V to +5.5 V 105 G = +2, VO = 2 V Step G = +2, VO = 2 V Step fC = 1 MHz, G = +2, VO = 2 V p-p fC = 5 MHz, G = +2, VO = 2 V p-p fC = 10 MHz, RL = 100 f = 10 kHz f = 10 kHz NTSC, G = +2, RL = 150 NTSC, G = +2, RL = 150 VCM = 1.0 V, SOIC Package SOIC Package TMIN to TMAX TMIN to TMAX VO = 1 V to 4 V (AD8065) VO = 1 V to 4 V (AD8066) 100 90 See Applications section VCM = 1 V to 4 V VCM = 1 V to 2 V (SOT23) RL = 1 k RL = 150 VO = 4 V p-p, SFDR -60 dBc, f = 500 kHz 30% Overshoot G = +1 74 78 0.1 to 4.85 0 to 2.4 0 to 5.0 100 91 0.03 to 4.95 0.07 to 4.83 35 75 5 PSRR 5 5.8 78 6.4 100 ABSOLUTE MAXIMUM RATINGS* MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . See Figure 2 Common-Mode Input Voltage . . VEE - 0.5 V to VCC + 0.5 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 1.8 V Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +125C Operating Temperature Range . . . . . . . . . . . -40C to +85C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The maximum safe power dissipation in the AD8065/AD8066 packages is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die will locally reach the junction temperature. At approximately 150C, which is the glass transition temperature, the plastic will change its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8065/ AD8066. Exceeding a junction temperature of 175C for an extended period of time can result in changes in the silicon devices, potentially causing failure. -4- REV. A AD8065/AD8066 MAXIMUM POWER DISSIPATION - W The still-air thermal properties of the package and PCB ( JA), ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature can be calculated as follows: 2.0 1.5 MSOP-8 SOIC-8 1.0 SOT23-5 0.5 TJ = TA + (PD x JA ) The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, then the total drive power is VS /2 IOUT, some of which is dissipated in the package and some in the load (VOUT IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = quiescent power + (total drive power - load power ) V V V PD = (VS x I S ) + S x OUT - OUT 2 RL RL 2 0 -60 -40 -20 0 20 40 60 AMBIENT TEMPERATURE - C 80 100 Figure 2. Maximum Power Dissipation vs. Temperature for a Four-Layer Board RMS output voltages should be considered. If RL is referenced to VS -, as in single-supply operation, then the total drive power is VS IOUT. If the rms signal levels are indeterminate, then consider the worst case, when VOUT = VS /4 for RL to midsupply: PD = (VS x I S ) + (VS /4)2 RL Airflow will increase heat dissipation effectively reducing JA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes, will reduce the JA. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps as discussed in the board layout section. Figure 2 shows the maximum safe power dissipation in the package versus the ambient temperature for the SOIC-8 (125C/W) and SOT23-5 (180C/W) packages on a JEDEC standard four-layer board. JA values are approximations. OUTPUT SHORT CIRCUIT In single-supply operation with RL referenced to VS- worst case is VOUT = VS /2. Shorting the output to ground or drawing excessive current for the AD8065/AD8066 will likely cause catastrophic failure. ORDERING GUIDE Model AD8065AR AD8065AR-REEL AD8065AR-REEL7 AD8065ART-REEL AD8065ART-REEL7 AD8066AR* AD8066AR-REEL7* AD8066AR-REEL* AD8066ARM-REEL AD8066ARM-REEL7 *Under development Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 5-Lead SOT23 5-Lead SOT23 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC MSOP MSOP 8-Lead SOIC Package Outline SOIC-8 SOIC-8 SOIC-8 SOT23-5 SOT23-5 SOIC-8 SOIC-8 SOIC-8 SOIC-8 MSOP-8 MSOP-8 SOIC-8 Branding Information HRA HRA 1 HAB HAB 1 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8065/AD8066 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. A -5- AD8065/AD8066-Typical Performance Characteristics (Default Conditions 24 G = +10 21 18 G = +5 15 6.6 VOUT = 0.7V p-p 5 V, CL = 5 pF, RL = 1 k , VOUT = 2 V p-p, Temperature = 25 C) VO = 200mV p-p 6.9 6.8 6.7 RL = 150 G = +2 VOUT = 0.2V p-p GAIN - dB GAIN - dB 12 9 G = +2 6 3 G = +1 0 -3 -6 0.1 6.5 6.4 6.3 6.2 6.1 6.0 5.9 0.1 VOUT = 1.4V p-p 1 10 FREQUENCY - MHz 100 1000 1 10 FREQUENCY - MHz 100 TPC 1. Small Signal Frequency Response for Various Gains TPC 4. 0.1 dB Flatness Frequency Response (See Test Circuit 2) 6 VO = 200mV p-p 4 G = +1 VS = 5V 9 VO = 200mV p-p G = +2 8 2 7 VS = 5V VS = 5V GAIN - dB GAIN - dB VS = 5V 0 VS = -2 12V 6 VS = 5 12V -4 4 -6 0.1 1 10 FREQUENCY - MHz 100 1000 3 0.1 1 10 FREQUENCY - MHz 100 1000 TPC 2. Small Signal Frequency Response for Various Supplies (See Test Circuit 1) TPC 5. Small Signal Frequency Response for Various Supplies (See Test Circuit 2) 2 1 G = +1 8 7 G = +2 VS = 5V VO = 2V p-p 0 GAIN - dB VS = 5V 6 VS = GAIN - dB VS = 12V 5V 5 4 3 -1 VS = -2 12V -3 -4 -5 0.1 2 1 0 0.1 1 10 FREQUENCY - MHz 100 1000 1 10 FREQUENCY - MHz 100 1000 TPC 3. Large Signal Frequency Response for Various Supplies (See Test Circuit 1) TPC 6. Large Signal Frequency Response for Various Supplies (See Test Circuit 2) -6- REV. A AD8065/AD8066 9 VO = 200mV p-p 6 G = +1 3 GAIN - dB 8 CL = 25pF CL = 20pF CL = 25pF Rsnub = 20 6 4 2 0 -2 -4 CL = 5pF CL = 55pF 0 CL = 5pF -3 GAIN - dB CL = 25pF -6 -6 G = +2 VO = 200mV p-p -9 0.1 1 10 FREQUENCY - MHz 100 1000 -8 0.1 1 10 FREQUENCY - MHz 100 1000 TPC 7. Small Signal Frequency Response for Various CLOAD (See Test Circuit 1) TPC 10. Small Signal Frequency Response for Various CLOAD (See Test Circuit 2) 8 VOUT = 0.2V p-p 6 4 2 VOUT = 2V p-p 8 R L = 100 7 6 5 R L = 1k 4 3 2 G = +2 1 G = +2 GAIN - dB 0 -2 -4 -6 -8 0.1 VOUT = 4V p-p GAIN - dB VO = 200mV p-p 1 10 FREQUENCY - MHz 100 1000 0 0 1 10 FREQUENCY - MHz 100 1000 TPC 8. Frequency Response for Various Output Amplitude (See Test Circuit 2) TPC 11. Small Signal Frequency Response for Various RLOAD (See Test Circuit 2) 14 12 10 8 GAIN - dB 6 4 2 0 G = +2 -2 -4 0.1 VO = 200mV p-p 1 10 FREQUENCY - MHz 100 1000 RF = RG = 1k , RS = 500 , CF = 3.3pF RF = RG = 1k , RS = 500 RF = RG = 500 , RS = 250 , CF = 2.2pF RF = RG = 500, RS = 250 80 120 60 OPEN-LOOP GAIN - dB PHASE 60 PHASE - Degrees 40 0 20 GAIN -60 0 -120 -20 0.01 0.1 1 10 FREQUENCY - MHz 100 -180 1k TPC 9. Small Signal Frequency Response for Various RF /CF (See Test Circuit 2) TPC 12. Open-Loop Response REV. A -7- AD8065/AD8066 -30 -40 G = +2 -40 -50 -50 -60 HD2 G = +2 DISTORTION - dBc HD2 R LOAD = 150 -70 -80 -90 HD2 R LOAD = 1k HD3 R LOAD = 1k HD3 R LOAD = 150 DISTORTION - dBc -60 -70 HD2 G = +1 -80 -90 HD3 G = +1 HD3 G = +2 -100 -110 -120 0.1 -100 1 10 FREQUENCY - MHz 100 -110 0.1 1 10 FREQUENCY - MHz 100 TPC 13. Harmonic Distortion vs. Frequency for Various Loads (See Test Circuit 2) TPC 16. Harmonic Distortion vs. Frequency for Various Gains (See Test Circuits 1 and 2) -30 -40 -50 G = +2 VS = 12V F = 1MHz -20 -30 -40 HD3 R LOAD = 150 HD2 R LOAD = 150 VS = 12V G = +2 HD2 VO = 20V p-p HD3 VO = 20V p-p DISTORTION - dBc -60 -70 -80 -90 DISTORTION - dBc -50 -60 -70 -80 -90 HD2 VO = 2V p-p HD3 VO = 2V p-p 1 FREQUENCY - MHz 10 HD2 VO = 10V p-p HD3 VO = 10V p-p -100 -110 -120 0 1 2 3 HD2 R LOAD = 300 HD3 R LOAD = 300 -100 -110 -120 0.1 4 5 6 7 8 9 10 11 12 13 14 15 OUTPUT AMPLITUDE - Vp-p TPC 14. Harmonic Distortion vs. Amplitude for Various Loads VS = 12 V (See Test Circuit 2) TPC 17. Harmonic Distortion vs. Frequency for Various Amplitudes (See Test Circuit 2) 50 VS = 45 12V RL = 100 100 INTERCEPT POINT - dBm 40 35 NOISE - nV/ Hz 10 FREQUENCY - MHz VS = 5V 10 30 VS = +5V 25 20 15 1 1 10 100 1k 10k 100k 1M FREQUENCY - Hz 10M 100M 1G TPC 15. Third Order Intercept vs. Frequency and Supply Voltage TPC 18. Voltage Noise -8- REV. A AD8065/AD8066 G = +1 CL = 5pF G = +1 CL = 20pF 50mV/DIV 20ns/DIV 50mV/DIV 20ns/DIV TPC 19. Small Signal Transient Response 5 V Supply (See Test Circuit 11) TPC 22. Small Signal Transient Response 5 V (See Test Circuit 1) G = +1 VS = 12V VOUT = 10V p-p VOUT = 4V p-p VOUT = 10V p-p G = +2 5s VS = 12V VOUT = 2V p-p VOUT = 2V p-p 2V/DIV 80ns/DIV 2V/DIV 80ns/DIV TPC 20. Large Signal Transient Response (See Test Circuit 1) TPC 23. Large Signal Transient Response (See Test Circuit 2) G= 1 IN OUT IN OUT G = +1 1.5V/DIV 100ns/DIV 1.5V/DIV 100ns/DIV TPC 21. Output Overdrive Recovery (See Test Circuit 3), VS = 5 V TPC 24. Input Overdrive Recovery (See Test Circuit 1), VS = 5 V REV. A -9- AD8065/AD8066 VIN = 140mV/DIV VIN = 500mV/DIV VOUT - 2 VIN +0.1% 0.1% t=0 -0.1% t=0 VOUT - 2 VIN 0.1% 2mV/DIV 64 s/DIV 2mV/DIV 10ns/DIV TPC 25. Long-Term Settling Time (See Test Circuit 8) TPC 28. 0.1% Short-Term Settling Time (See Test Circuit 8) 0 -5 INPUT BIAS CURRENT - pA -Ib -10 42 36 30 24 18 12 6 0 5 0 -5 BJT INPUT STAGE +Ib -Ib Ib - A FET INPUT STAGE -Ib -15 -25 -30 Ib - pA -20 +Ib -10 -15 -25 -20 +Ib 25 35 45 55 65 TEMPERATURE - C 75 85 -30 -12 -10 -8 -6 -4 -2 2 4 0 6 COMMON-MODE VOLTAGE - V 8 10 12 TPC 26. Input Bias Current vs. Temperature TPC 29. Input Bias Current vs. Common-Mode Voltage Range* 40 35 N = 299 SD = 0.388 MEAN = -0.069 0.3 VS = 12V 0.2 OFFSET VOLTAGE - mV 30 0.1 VS = 0 5V VS = +5V 25 20 15 -0.1 10 -0.2 5 0 -2.0 -0.3 -14 -12 -10 -8 -6 -4 -2 0 2 4 68 COMMON-MODE VOLTAGE - V 10 12 14 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 INPUT OFFSET VOLTAGE - mV TPC 27. Input Offset Voltage vs. Common-Mode Voltage TPC 30. Input Offset Voltage *See Input and Output Overload Behavior section. -10- REV. A AD8065/AD8066 -30 100 -40 10 OUTPUT IMPEDANCE - -50 CMRR - dB -60 -70 -80 -90 VS = 12V 1 G = +2 0.1 G = +1 0.01 VS = 5V -100 0.1 1 10 FREQUENCY - MHz 100 0 100 1k 10k 100k 1M 10M 100M FREQUENCY - Hz TPC 31. CMRR vs. Frequency (See Test Circuit 5) TPC 34. Output Impedance vs. Frequency (See Test Circuits 4 and 6) 0.30 OUTPUT SATURATION VOLTAGE - mV 80 75 70 65 60 55 50 45 40 35 30 25 35 45 55 65 TEMPERATURE - C 75 85 VOL - VEE VCC - VOH OUTPUT SATURATION VOLTAGE - V 0.25 VCC - VOH 0.20 0.15 0.10 VOL - VEE 0.05 0 0 10 20 I LOAD - mA 30 40 TPC 32. Output Saturation Voltage vs. Output Load Current TPC 35. Output Saturation Voltage vs. Temperature 0 -10 -20 -30 PSRR - dB -40 -50 -60 -70 -80 -90 -100 0.01 0.1 1 10 FREQUENCY - MHz 100 1000 - PSRR + PSRR CROSSTALK - dB 0 -10 -20 -30 -40 -50 B TO A -60 -70 A TO B -80 -90 0.1 VIN = 2V p-p G = +1 1 10 FREQUENCY - MHz 100 TPC 33. PSRR vs. Frequency (See Test Circuits 7 and 9) TPC 36. CrossTalk vs. Frequency (See Test Circuit 10) REV. A -11- AD8065/AD8066 6.60 VS = 6.55 VS = 5V 12V 120 125 VS = 115 OPEN-LOOP GAIN - dB 12V SUPPLY CURRENT - mA 6.50 110 105 100 95 6.45 VS = +5V 6.40 VS = +5V VS = 5V 6.35 90 6.30 6.25 -40 85 80 -20 0 20 40 TEMPERATURE - C 60 80 0 10 20 I LOAD - mA 30 40 TPC 37. Quiescent Supply Current vs. Temperature for Various Supply Voltages TPC 38. Open-Loop Gain vs. Load Current for Various Supply Voltages Test Circuits SOIC Pinout +VCC 4.7 F +VCC 4.7 F 0.1 F 0.1 F 24.9 499 2.2pF 499 Rsnub AD8065 VIN 49.9 0.1 F 1k FET PROBE AD8065 VIN CLOAD Rsnub FET PROBE 249 49.9 0.1 F 1k CLOAD 4.7 F 4.7 F -VEE -VEE Test Circuit 1. G = +1 Test Circuit 2. G = +2 -12- REV. A AD8065/AD8066 +VCC 4.7 F +VCC 4.7 F 0.1 F 0.1 F 2.2pF 499 49.9 FET PROBE AD8065 49.9 249 0.1 F 1k 499 499 0.1 F 1k VIN AD8065 FET PROBE 499 499 499 VIN 4.7 F 4.7 F -VEE -VEE Test Circuit 3. G = -1 +VCC 4.7 F Test Circuit 5. CMRR +VCC 4.7 F 0.1 F 0.1 F 24.9 499 499 AD8065 NETWORK ANALYZER S22 249 AD8065 NETWORK ANALYZER S22 0.1 F 0.1 F 4.7 F 4.7 F -VEE -VEE Test Circuit 4. Output Impedance G = +1 Test Circuit 6. Output Impedance G = +2 REV. A -13- AD8065/AD8066 +VCC 4.7 F VIN 1V p-p 0.1 F +VCC 49.9 24.9 24.9 FET PROBE AD8065 FET PROBE AD8065 1k 49.9 1k 0.1 F 4.7 F VIN 1V p-p -VEE -VEE Test Circuit 7. Positive PSRR Test Circuit 9. Negative PSRR +VCC 24.9 4.7 F 0.1 F FET PROBE 24.9 2.2pF 499 499 +5V 4.7 F 1K 0.1 F RECEIVE SIDE 976 AD8065 VIN 249 49.9 0.1 F TO SCOPE 49.9 VIN 0.1 F 1K 49.9 4.7 F 4.7 F -5V -VEE DRIVE SIDE Test Circuit 8. Settling Time Test Circuit 10. CrossTalk - AD8066 -14- REV. A AD8065/AD8066 2.2pF 499 499 5V 1.5V 4.7 F 0.1 F FET PROBE 249 VIN 1K 49.9 1.5V 1.5V Test Circuit 11. Single Supply REV. A -15- AD8065/AD8066 THEORY OF OPERATION Noninverting Closed-Loop Frequency Response The AD8065/AD8066 are voltage feedback operational amplifiers that combine a laser-trimmed JFET input stage with Analog Devices' eXtra Fast Complementary Bipolar process, resulting in an outstanding combination of precision and speed. Supply voltage range is from 5 V to 24 V. The amplifiers feature a patented rail-to-rail output stage capable of driving within 0.5 V of either power supply while sourcing or sinking up to 30 mA. Also featured is a single-supply input stage that handles common-mode signals from below the minus supply to within 3 V of the positive rail. Operation beyond the JFET input range is possible because of an auxiliary bipolar input stage that functions with input voltages up to the positive supply. The amplifiers operate as if they have a rail-to-rail input and exhibit no phase reversal behavior for common-mode voltages within the power supply. With voltage noise of 7 nV/Hz and -88 dBc distortion for 1 MHz 2 V p-p signals, the AD8065 is a great choice for high resolution data acquisition systems. Its low noise, sub-pA input current, precision offset, and high speed make it a superb preamp for fast photodiode applications. The speed and output drive capability of the AD8065 also make it useful in video applications. Closed-Loop Frequency Response Solving for the transfer function: VO 2 x fcrossover (RG + RF ) = VI (RF + RG )s + 2 x fcrossover x RG fcrossover = the frequency where the amplifier's open-loop gain equals 0 db. At dc: VO RF + RG = VI RG Closed-loop -3 dB frequency: f - 3 dB = fcrossover x Inverting Configuration RG RF + RG VO -2 x fcrossover x RF = VI s(RF + RG ) + 2 x fcrossover x RG At dc: VO R =- F VI RG The AD8065/AD8066 are classic voltage feedback amplifiers with an open-loop frequency response that can be approximated as the integrator response shown in Figure 3. Basic closed-loop frequency response for inverting and noninverting configurations can be derived from the shown schematics. Closed-loop -3 dB frequency: f - 3 dB = fcrossover x RG RF + RG RF RG VI VE A VO VI RG VE RF A VO 80 A = (2 Pi fcrossover)/s OPEN-LOOP GAIN (A) - dB 60 40 20 fcrossover = 65MHz 0 0.01 0.1 1 FREQUENCY - MHz 10 100 Figure 3. Open-Loop Gain vs. Frequency and Basic Connections -16- REV. A AD8065/AD8066 The closed-loop bandwidth is inversely proportional to the noise gain of the op amp circuit, (RF + RG)/RG. This simple model is accurate for noise gains above 2. The actual bandwidth of circuits with noise gains at or below 2 will be higher than those predicted with this model due to the influence of other Also see TPCs 13 through 17. The lowest distortion will be obtained with the AD8065 used in low gain inverting applications, since this eliminates common-mode effects. Higher closed-loop gains result in worse distortion performance. Input Protection poles in the frequency response of the real op amp. RF +VOS - Ib- A VO RG RS The inputs of the AD8065 are protected with back-to-back diodes between the input terminals as well as ESD diodes to either power supply. This results in an input stage with pico amps of input current that can withstand up to 1500 V ESD events (human body model) with no degradation. Excessive power dissipation through the protection devices will destroy or degrade the performance of the amplifier. Differential voltages greater than 0.7 V will result in an input current of approximately (|V+ - V-|- 0.7 V)/RI, where RI is the resistance in series with the inputs. For input voltages beyond the positive supply, the input current will be approximately (VI - VCC - 0.7)/RI. Beyond the negative supply, the input current will be about (VI - VEE + 0.7)/R I. If the inputs of the amplifier are to be subjected to sustained differential voltages greater than 0.7 V or to input voltages beyond the amplifier power supply, input current should be limited to 30 mA by an appropriately sized input resistor (RI) as shown in Figure 5. RI> (| V+- V- | - 0.7V) 30mA FOR LARGE | V+ - V- | RI RI> (VI - VEE - 0.7V) 30mA RI> (VI - VEE +0 .7V) 30mA FOR VI BEYOND SUPPLY VOLTAGES VO VI Ib+ Figure 4. Voltage Feedback Amplifier DC Errors Figure 4 shows a voltage feedback amplifier's dc errors. For both inverting and noninverting configurations: R + RF RG + RF VO (error) = - Ib + RS G + Ib - RF + VOS R RG G The voltage error due to Ib+ and Ib- is minimized if RS = RF RG (though with the AD8065's input currents at less than 20 pA overtemperature, this is likely not a concern). To include common-mode and power supply rejection effects, total VOS can be modeled as: VOS = VOSnom + VS Vcm + PSR CMR AD8065 VI VOSnom is the offset voltage specified at nominal conditions. VS is the change in power supply from nominal conditions. PSR is power supply rejection. VCM is the change in common-mode voltage from nominal conditions. CMR is common-mode rejection. Wideband Operation Figure 5. Current Limiting Resistor Thermal Considerations Test Circuits 1, 2, and 3 show the circuits used for wideband characterization for gains of +1, +2, and -1. Source impedance at the summing junction (RF R G) will form a pole in the amplifier's loop response with the amplifier's input capacitance of 6.6 pF. This can cause peaking and ringing if the time constant formed is too low. Feedback resistances of 300 to 1 k are recommended, since they will not unduly load down the amplifier and the time constant formed will not be too low. Peaking in the frequency response can be compensated with a small capacitor (CF) in parallel with the feedback resistor, as illustrated in TPC 9 in typical characteristics. This shows the effect of different feedback capacitances on the peaking and bandwidth for a noninverting G = +2 amplifier. For the best settling times and the best distortion, the impedances at the AD8065 input terminals should be matched. This minimizes nonlinear common-mode capacitive effects that can degrade ac performance. Actual distortion performance depends on a number of variables: * The closed-loop gain of the application * Whether it is inverting or noninverting * Amplifier loading * Signal frequency and amplitude * Board layout REV. A With 24 V power supplies and 6.5 mA quiescent current, the AD8065 dissipates 156 mW with no load. The AD8066 dissipates 312 mW. This can lead to noticeable thermal effects, especially in the small SOT23-5 (thermal resistance of 160 C W). VOS temperature drift is trimmed to guarantee a max drift of 17 V C, so it can change up to 0.425 mV due to warm-up effects for an AD8065 in a SOT23-5 package on 24 V. Ib increases by a factor of 1.7 for every 10 C rise in temperature. Ib will be close to 5 times higher at 24 V supplies as opposed to a single 5 V supply. Heavy loads will increase power dissipation and raise the chip junction temperature as described in the maximum power dissipation section. Care should be taken to not exceed the rated power dissipation of the package. Input and Output Overload Behavior The AD8065 has internal circuitry to guard against phase reversal due to overdriving the input stage. A simplified schematic of the input stage, including the input-protection diodes and antiphase reversal circuitry, is shown in Figure 6. The circuit is arranged such that when the input common-mode voltage exceeds a certain threshold, the input JFET pair's bias current will turn OFF, and the bias current of an auxiliary NPN pair will turn ON, taking over control of the amplifier. When the input common-mode voltage returns to a viable operating value, the FET stage turns back ON, the NPN stage turns OFF, and normal operation resumes. -17- AD8065/AD8066 The NPN pair can sustain operation with the input voltage up to the positive supply, so this is a pseudo rail-to-rail input stage. For operation beyond the FET stage's common-mode limit, the amplifier's VOS will change to the NPN pair's offset (mean of 160 V, standard deviation of 820 V), and Ib will increase to the NPN pair's base current up to 45 A (see TPC 29). Switchback, or recovery time, is about 100 ns, as shown in TPC 24. The output transistors of the rail-to-rail output stage have circuitry to limit the extent of their saturation when the output is overdriven. This helps output recovery time. Output recovery from a 0.5 V output overdrive on a 5 V supply is shown in TPC 21. LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS Power Supply Bypassing to implementing effective high speed circuit design. The length of the current path is directly proportional to the magnitude of parasitic inductances and thus the high frequency impedance of the path. High speed currents in an inductive ground return will create an unwanted voltage noise. The length of the high frequency bypass capacitor leads is most critical. A parasitic inductance in the bypass grounding will work against the low impedance created by the bypass capacitor. Place the ground leads of the bypass capacitors at the same physical location. Because load currents flow from the supplies as well, the ground for the load impedance should be at the same physical location as the bypass capacitor grounds. For the larger value capacitors, which are intended to be effective at lower frequencies, the current return path distance is less critical. Leakage Currents Power supply pins are actually inputs and care must be taken so that a noise-free stable dc voltage is applied. The purpose of bypass capacitors is to create low impedances from the supply to ground at all frequencies, thereby shunting or filtering a majority of the noise. Decoupling schemes are designed to minimize the bypassing impedance at all frequencies with a parallel combination of capacitors. 0.1 F (X7R or NPO) chip capacitors are critical and should be as close as possible to the amplifier package. The 4.7 F tantalum capacitor is less critical for high frequency bypassing, and in most cases, only one per board is needed at the supply inputs. Grounding A ground plane layer is important in densely packed PC boards to spread the current minimizing parasitic inductances. However, an understanding of where the current flows in a circuit is critical Poor PC board layout, contaminants, and the board insulator material can create leakage currents that are much larger than the input bias current of the AD8065. Any voltage differential between the inputs and nearby runs will set up leakage currents through the PC board insulator. For example: 1 V/100 G = 10 pA. Similarly any contaminants on the board can create significant leakage (skin oils are a common problem). To significantly reduce leakages put a guard ring (shield) around the inputs and input leads that are driven to the same voltage potential as the inputs. This way there is no voltage potential between the inputs and surrounding area to set up any leakage currents. For the guard ring to be completely effective it must be driven by a relatively low impedance source and should completely surround the input leads on all sides, above and below using a multilayer board. VCC TO REST OF AMP VTHRESHOLD VBIAS VN VP S S VEE Figure 6. Simplified Input Stage -18- REV. A AD8065/AD8066 Another effect that can cause leakage currents is the charge absorption of the insulator material itself. Minimizing the amount of material between the input leads and the guard ring will help to reduce the absorption. Also, low absorption materials, such as Teflon(R) or ceramic, may be necessary in some instances. Input Capacitance 1) As shown in Figure 7, put a small value resistor (RS) in series with the output to isolate the load capacitor from the amp's output stage. Twenty ohms is a good value to choose (see TPC 7). Along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. A few pF of capacitance will reduce the input impedance at high frequencies, in turn increasing the amplifiers' gain, causing peaking of the frequency response or even oscillations, if severe enough. It is recommended that the external passive components, that are connected to the input pins, be placed as close as possible to the inputs to avoid parasitic capacitance. The ground and power planes must be kept at a small distance away from the input pins on all layers of the board. Output Capacitance AD8065 VI RS = 20 C1 VO Figure 7. Output Isolation Resistor 2) Increase the phase margin with higher noise gains or adding a pole with a parallel resistor and capacitor from -IN to the output. Input-to-Output Coupling To a lesser extent, parasitic capacitances on the output can cause peaking and ringing of the frequency response. There are two methods to effectively minimize their effect. The output signal traces should not be parallel with inputs in order to minimize capacitive coupling between the inputs and output. CF RF IPHOTO CS VB RSH = 10^11 CD CM CM CF + CS RF VO Figure 8. Wideband Photodiode Preamp Teflon is a registered trademark of E.I. duPont de Nemours and Company. REV. A -19- AD8065/AD8066 Wideband Photodiode Preamp f( 45 ) = Figure 8 shows an I/V converter with an electrical model of a photodiode. The basic transfer function is: fCR 2 x RF x CS fCR = the amplifier crossover frequency RF = the feedback amplifier CS = the total capacitance at the amplifier summing junction (amplifier + photodiode + board parasitics) The value of CF that produces f(45) can be shown to be: CF = CS 2 x RF x fCR VOUT = I PHOTO x RF 1 + sCF RF where IPHOTO is the output current of the photodiode, and the parallel combination of RF and CF set the signal bandwidth. The stable bandwidth attainable with this preamp is a function of RF, the gain bandwidth product of the amplifier, and the total capacitance at the amplifier's summing junction, including CS and the amplifier input capacitance. R F and the total capacitance produce a pole in the amplifier's loop transmission that can result in peaking and instability. Adding CF creates a zero in the loop transmission that compensates for the pole's effect and reduces the signal bandwidth. It can be shown that the signal bandwidth resulting in a 45C phase margin (f(45)) is defined by the expression: The frequency response in this case will show about 2 dB of peaking and 15% overshoot. Doubling CF and cutting the bandwidth in half will result in a flat frequency response, with about 5% transient overshoot. The preamp's output noise over frequency is shown in Figure 9. Table I. RMS Noise Contributions of Photodiode Preamp Contributor RF ( 2) Amp to f1 Expression RMS Noise with RF = 50 k, CS = 15 pF, CF = 2 pF 64.5 V 2.4 V 2 x 4 kT x RF x f 2 x 1.57 ven x ven x f1 ( CS + C M + C F + 2 C D ) x CF f 2 - f1 Amp (f2-f1) 31 V Amp (past f2) ven x (CS + CM + CD + 2 CF ) CF Total x f 3 x 1.57 260 V 270 V -20- REV. A AD8065/AD8066 f1 = 2 R (C + C + C + 2C ) F F S M D f2 = 2 R C FF fCR f3 = (C + C + 2C + C ) /C S M D F F 1 1 VOLTAGE NOISE - nV/ Hz bandwidth extends past the preamp signal bandwidth and is eventually rolled off by the decreasing loop gain of the amplifier. Keeping the input terminal impedances matched is recommended to eliminate common-mode noise peaking effects, which will add to the output noise. Integrating the square of the output voltage noise spectral density over frequency and then taking the square root allows users to obtain the total rms output noise of the preamp. Table I summarizes approximations for the amplifier and feedback and source resistances. Noise components for an example preamp with RF = 50 k, CS = 15 pF, and CF = 2 pF (bandwidth of about 1.6 MHz) are also listed. High Speed JFET Input Instrumentation Amplifier RF NOISE f2 f1 VEN VEN (CF + CS + CM + 2CD) /CF f3 NOISE DUE TO AMPLIFIER Figure 10 shows an example of a high speed instrumentation amplifier with high input impedance using the AD8065. The dc transfer function is: 1 + 1000 VOUT = (VN - VP ) RG FREQUENCY - Hz Figure 9. Photodiode Voltage Noise Contributions The pole in the loop transmission translates to a zero in the amplifier's noise gain, leading to an amplification of the input voltage noise over frequency. The loop transmission zero introduced by CF limits the amplification. The noise gain's VCC 0.1 F RS1 VN 1/2 4.7 F AD8066 4.7 F 2.2pF 0.1 F VEE R2 500 VCC R1 500 RF = 500 0.1 F 4.7 F AD8065 4.7 F VO RG 0.1 F R3 RF = 500 500 VEE VCC 0.1 F 4.7 F 2.2pF R4 500 1/2 RS2 VP AD8066 4.7 F 0.1 F VEE Figure 10. High Speed Instrumentation Amplifier REV. A -21- AD8065/AD8066 For G = +1, it is recommended that the feedback resistors for the two preamps be set to a low value (for instance 50 for 50 source impedance). The bandwidth for G = +1 will be 50 MHz. For higher gains, the bandwidth will be set by the preamp, equaling: Inamp - 3 dB = ( fCR x RG ) / (2 x RF ) Video Buffer The output current capability and speed of the AD8065 make it useful as a video buffer, shown in Figure 11. The G = +2 configuration compensates for voltage division of the signal due to the signal termination. This buffer maintains 0.1 dB flatness for signals up to 7 MHz, from low amplitudes up to 2 V p-p (TPC 4). Differential gain and phase have been measured to be 0.02%, 0.028 at 65 V supplies. VS 4.7 F 75 VI AD8065 75 0.1 F VS 2.2pF 4.7 F VO Common-mode rejection of the inamp will be primarily determined by the match of the resistor ratios R1:R2 to R3:R4. It can be estimated: VO (1 - 2) = VCM (1 + 1) 2 The summing junction impedance for the preamps is equal to RF 0.5(RG). This is the value to be used for matching purposes. 249 0.1 F 499 499 Figure 11. Video Buffer -22- REV. A AD8065/AD8066 OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] (R-8) Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 8 5 4 4.00 (0.1574) 3.80 (0.1497) PIN 1 1 6.20 (0.2440) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.19 (0.0075) 0.50 (0.0196) 0.25 (0.0099) 45 0.51 (0.0201) 0.33 (0.0130) 1.27 (0.0500) 0.41 (0.0160) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-012AA 5-Lead Surface-Mount Package [SOT23]* (RT-5) Dimensions shown in millimeters 2.90 8-Lead MSOP (RM-8) Dimensions shown in millimeters 3.00 BSC 5 4 8 5 1.60 BSC 1 2 3 2.80 BSC 3.00 BSC 1 4 4.90 BSC PIN 1 0.95 BSC 1.30 1.15 0.90 1.90 BSC PIN 1 0.65 BSC 0.15 0.00 1.10 MAX 8 0 0.80 0.40 1.45 MAX 10 0 0.38 0.22 0.22 0.08 0.60 0.45 0.30 0.23 0.08 SEATING PLANE 0.15 MAX 0.50 0.30 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187AA COMPLIANT TO JEDEC STANDARDS MO-178AA *Under development REV. A -23- AD8065/AD8066 Revision History Location 8/02--Data Sheet changed from REV. 0 to REV. A. Page Added AD8066 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 New Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to TPCs 18, 25, and 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 New TPC 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Added Test Circuits 10 and 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MSOP (RM-8) added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 C02916-0-8/02(A) PRINTED IN U.S.A. Added SOIC-8 (R) and MSOP-8 (RM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -24- REV. A |
Price & Availability of AD8065
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